The Xilinx Gigabit Ethernet MAC core is part of the FPGA SystemIO solution. SystemIO interfaces provide high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The MAC core performs the Link function of the Gigabit Ethernet standard. The core can interface to an off-chip PHY using the core's Gigabit Media Independent Interface (GMII) or RGMII.

Key Features

• Single-speed duplex 1 Gbps MAC controller
• Designed to IEEE 802.3-2002
• Choice of GMII, RGMII interface options :
  • 8b GMII interface running 125MHz for 1Gbps bandwidth
    • 8b wide interface in both Tx and Rx directions
  • RGMII interface running at 125MHz for 1Gbps bandwidth
    • 4-bit wide DDR interface in both RX and TX direction
  • Allows direct interfacing between Xilinx FPGAs and industry standard ASSP PHY devices
• 8-bit internal data path and back-end interface
  • 125MHz operation
• Cut-through operation with minimum buffering for maximum flexibility in 8-bit client bus interfacing
• Configured and monitored through an independent microprocessor-neutral interface
• Flexible and powerful Ethernet Statistics vector that interfaces with Xilinx Ethernet Statistics Core
• Optional Address Filter with a selectable number of Address Table entries
• Optional flow control through MAC Control pause frames; symmetrically or asymmetrically enabled 
• MDIO interface to managed objects in PHY layer.
• Optional support of VLAN frames designed to IEEE 802.3-2002 specification
• Programmable Interframe Gap
• Optional support of “jumbo frames” of any length
• Available under terms of the SignOnce IP License