XC5200

As an alternative to "gate counting", the capacity of look-up-table-based FPGAs can be measured more directly and objectively by examining the number of available "logic cells".

本应用指南介绍了使用 Alliance 系列软件实现 HDL 仿真时需注意的基本流程和问题。 本技术文档的目的是让用户熟悉一些概念，它不可替代 Xilinx 或 HDL 仿真器的技术文档。

本应用指南介绍了成熟的Xilinx产品系列，并着重讲述了其相互区别。

在Spartan™ XC3000、XC4000和XC5200器件系列中，Xilinx提供了现场可编程门阵列（FPGA）的扩展和兼容产品。本简介介绍了Xilinx FPGA的2方面：给客户提供了哪些逻辑资源，以及如何对器件进行编程。

Clarifies why the overshoot/undershoot limit includes both magnitude and duration. Applies to mature FPGA families only.

Beware of hold time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates.

All Xilinx SRAM-based FPGAs can be in-system configured and reconfigured an unlimited number of times. This application note describes the procedures for reconfiguring mature Xilinx FPGAs.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Xilinx FPGA 可在普通的菊花链结构中进行配置，在那里主器件生成 CCLK 脉冲，并将串行配置信息输入下一个下行器件，该下行器件进一步将数据输入下一个下行器件，以此类推。 菊花链中的器件数量没有限制，XC3000™、XC4000™、Spartan™ 和 XC5200™ 系列器件可以自由组合，但只有一个约束条件：主器件需为该链中最高位系列的器件之一。

这些指南针对所有 XC3000™、XC4000™、XC5200™ 和 Spartan™ FPGA 器件及其衍生产品介绍了配置步骤。一般用户无须了解或记住所有细节，但出现问题时应参考调试提示。

This application note reviews the differences between the XC5200™ and XC2000™/XC3000™ families, recommends approaches for converting XC2000/XC3000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.

This application note reviews the differences between the XC5200™ and XC4000™ families, recommends approaches for converting XC4000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.

The phase comparator described in this application note permits phase-locked loops to be constructed using FPGA devices that require only an external voltage-controlled oscillator and integrating amplifier.

本应用指南讨论了在 FPGA 器件中实现状态机的多种现有方法，特别是针对中型状态机的一位热码编码方法。

XC4000/XC5200/Spartan FPGA 器件具有符合 IEEE 1149.1 标准的边界扫描工具。本应用指南详细介绍了这些工具，并解释了如何将边界扫描加入 FPGA 设计中。

This fully synchronous, non-loadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small longline delay is eliminated, resulting in the fastest possible synchronous counter.