16 channel, LVDS, 4:1 Deserialization, SDR. This design demonstrates the operation of an SFI-4 physical interface in Virtex-4 at the key SFI-4 rates of 622, 644, and 700 Mbits/s. The source synchronous alignment scheme used is bus alignment, meaning that all 16 data channels are treated as one channel and aligned at the same time. This assumes minimal skew between channels. There is no training pattern for this design.