Xilinx® device architectures include several configurable functional blocks – including clocking, digital signal processing, and high-speed I/O blocks – that provide you with advanced functionality. Typically, these blocks are fairly complex in their operation and yet very flexible, so parameterizing them for the desired behavior can be a daunting and time-consuming task if done by hand.

The architecture wizards found in the ISE™ Foundation™ design environment can streamline the process of customizing such blocks. There are several wizards available; each one leads you through a sequence of screens that allows you to precisely define the behavior of the block at hand. Each screen has built-in design rule checking that ensures that the result will be “correct by construction” – that is, that the combination of selections made is a legal configuration of the target block.

After selecting “Finish” on the final screen, the wizard creates a customized block definition file (filename.xaw). ISE Foundation software then translates that definition into a HDL description of the block and creates a corresponding HDL instantiation template that you can then use in your design.

The Clocking Wizard
As an example, let’s use the clocking wizard to create a digital clocking manager module for a Virtex™-4 FPGA, which will be driven by a clock source external to the device. It will generate a main clock signal, as well as a frequency-doubled clock that drives an enabled buffer. A LOCKED signal will indicate when the DCM clock signal has stabilized after the FPGA is powered up or reset.

Examining the resulting HDL code and instantiation template generated by ISE Foundation software after the wizard finishes clearly shows the benefit of using an architecture wizard for this type of task.

Starting the Clocking Wizard
From within ISE’s Project Navigator, we start the clocking wizard by selecting “Add New Source” and selecting the “IP (CoreGen and Architecture Wizard)” source type. The resulting dialog will let us select the “Single DCM ADV v8.1i” variant (see Figure 1). Pressing “Next” and “Finish” on the subsequent dialog boxes invokes the clocking wizard.

General Setup Screen
On the first clocking wizard screen, we select the desired inputs and outputs of the block, the clock source, phase shift type, frequency, and feedback configuration (Figure 2).

Clock Buffers Screens
Selecting “Next” takes us to the clock buffers screen. By default, all clock outputs drive global buffers, but for our design, we need to place an enabled buffer after the frequency-doubled clock output. To do this, we select “Customize Buffers” and then click the “Global Buffer” button next to CLK2X to change its global buffer to an enabled buffer (Figure 3).

Using the “Add Buffer” button on the next screen, we place an enabled buffer at the block’s clock input (Figure 4).

Summary Screen
After creating the buffer by pressing the “OK” button, we click the “Next” button on the clock buffers screen to advance to the summary page, which provides a detailed report on the block that will be generated (Figure 5).

Selecting the “Finish” button creates a binary filename.xaw source file in the ISE Foundation project directory. The .xaw will automatically be converted by ISE Foundation software to the corresponding HDL description required for synthesis when you implement your design, but you can view that HDL at any time after the .xaw file has been created. Either VHDL or Verilog is available; VHDL is shown in our example.

Here is where you can really see the true value of the architecture wizard – imagine having to write this code by hand:
HDL sample code

The preceding HDL source code describes the DCM module to the synthesis tool that we are using, but we will still need to create an instance of the module in our design. This is achieved with an “instantiation template,” which is created by using the “View HDL Instantiation Template” process in Project Navigator. The resulting code snippet can be inserted into our design to create an instance of the DCM module:
code snippet

Supported Block Configurations
The above example illustrates only a single configuration of one type of block that the architecture wizards support. Other supported blocks and configurations include:

Clocking Wizard
The digital clock management module provides you with extensive control over the global clocking configuration(s) in your design and features the choice of either an external or internal clock source, clock deskew, phase shift control, and frequency synthesis.

The clocking wizard can create several DCM configurations using one or more DCM modules:

• Single DCM
• Single DCM_ADV
• Clock forwarding/board deskew
• Board deskew with an internal deskew
• Clock switching with two DCMs
• Cascading in series with two DCMs
• PMCD (Virtex-4 FPGAs)

Rocket IO Wizard
The Xilinx Rocket IO™ wizard configures the multi-gigabit transceiver block in Virtex-II Pro and Virtex-II Pro X devices (Virtex-4 Rocket IO support is found in CORE Generator™ software). For certain protocols, it also allows the configuration of multiple channels of transceivers. For Virtex-II Pro devices, the following Rocket IO protocols are available through the wizard:

• Fibre Channel
• Gigabit Ethernet
• XAUI
• Infiniband
• Aurora
• PCI Express
• SONET OC-48 (Virtex-II Pro X devices)
• SONET OC-192 (Virtex-II Pro X devices)
• Custom user-defined configurations Xtreme DSP Wizard (Virtex-4 Devices)

• Multiplier
• Accumulator
• Multiplier-accumulator (MAC)
• Adder/subtractor

• The memory applications mode configures a block of I/O for memory application usage. The wizard allows you to set up the data bus and clocks/strobes, including specifying delay information. You can also configure the address bus, reference clocks, and control signals.
• The non-memory applications mode configures a block of I/O for nonmemory application usage, such as for networking cases. The wizard allows you to set up the data bus and clocks, including specifying delay information. You can also configure reference clocks and control signals.

The architecture wizards augment other Xilinx IP block creation tools such as Platform Studio, CORE Generator software, and System Generator for DSP – all of which help you to get your product to market as quickly as possible.

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