When Xilinx invented the FPGA in the mid 1980s, the preferred way to verify a design was to program the FPGA in the actual system and see if it operated properly from both a timing and functional standpoint.

Those days are long gone.

According to a 2005 EDA study by CMP Media, verification is one of the top three considerations for FPGA designers. A fast and successful verification experience is essential to get your product to market on time. But how do you know if your current flow is the best choice, especially for today’s high-density FPGAs? At a minimum, a sound verification strategy should include static/dynamic timing and dynamic simulation. Optional advanced methodologies such as equivalency checking and assertionbased verification are now also available to Xilinx FPGA users (Figure 1).

In this article, we’ll discuss improvements and additions to the verification solutions available from Xilinx and its Alliance Program Members.

Improved Timing Analysis in ISE 8.1i Software
A complete timing verification must include checking the FPGA design under both the best- and worst-case operating conditions. The worst-case conditions occur when the voltage supply to the FPGA is at a minimum and the temperature of the FPGA is at a maximum. These conditions increase the internal delays of the device, and thus increase the potential for setup time violations. The best-case conditions occur when the voltage supply to the FPGA is at a maximum and the temperature of the FPGA is at a minimum.

These conditions decrease the internal delays of the device and increase the potential for hold-time violations. In addition to voltage and temperature variations, the clock system is subject to uncertainty because of various sources of jitter throughout the system. Jitter can cause the early or late arrival of a clock edge and thus increase the chance of a setup or hold-time error.

Traditionally, FPGA-based static timing analysis software has only been able to analyze device operation under worst-case temperature and voltage conditions without regard to clock uncertainty. Although this methodology was sufficient for slower system-level interface standards, the increasing speed of today’s dual-data-rate (DDR) source-synchronous interface standards demands a more complete verification solution.

STA Analysis for Real-World Conditions
To provide the most accurate timing verification, Xilinx® static timing analysis software automatically analyzes the design under the best- and worst-case operating conditions. This analysis is performed simultaneously for the both the system I/O interface and the internal logic of the design. The methodology uses a combination of minimum and maximum delays for setup and hold-time analysis. In setup time analysis, the worst-case condition occurs when the data path delay is at a maximum and the clock path delay is at a minimum. Conversely, the worst-case hold-time analysis condition occurs when the data path delay is at a minimum and the clock path delay is at a maximum.

To account for clock uncertainty in the design, the Xilinx software system allows the specification of the input jitter for each clock. In addition to the incoming clock jitter, the clock uncertainty because of system jitter and the clocking system design automatically takes into account all timing analysis checks. Clock uncertainty increases the potential for a setup time violation by effectively decreasing the clock path delay. In the same manner, clock uncertainty increases the chance of a hold-time violation by increasing the clock path delay.

By providing the ability to simultaneously model both the minimum and maximum delays of the clock and data paths, Xilinx timing analysis software ensures the greatest reliability of your system design across all operating conditions (Figure 2).

ISE 8.1i Software Breaks New Ground
Although static timing analysis verifies that the physical delays of data and clock paths in the FPGA design will not cause setup or hold-time violations, you must also verify the design’s functional operation. Because of the dynamic nature of the design, the functional timing operation must be tested at system-level speeds. In a manner similar to static timing analysis, for an accurate timing simulation you must take into account the best- and worst-case conditions due to process, voltage, temperature, and clock uncertainty. Xilinx ISE™ 8.1i software breaks new ground in dynamic timing simulation accuracy by allowing both minimum and maximum clock and path delays to be simulated simultaneously. This unique ability ensures that setup and hold-time violations will be accurately accounted for, and works automatically with all simulators.

Easy-to-Use Simulators from Xilinx

ModelSim Xilinx Edition III
Working with the Model Technology division of Mentor Graphics, Xilinx has developed a customized, lower cost version of the popular ModelSim PE simulator called ModelSim Xilinx Edition III (MXE III) (Figure 3). MXE III is ideal for mediumdensity FPGAs with capacities as high as 2 million system gates, such as the Spartan™-3E FPGA family. It enables you to verify the functional and timing models of your design and your HDL source code (for more information, see www.xilinx.com/ise). A lower performance version of MXE III called ModelSim Starter is a no-charge feature of the ISE Foundation™ toolset.

MXE III’s features and capabilities include:

• Seamless integration with ISE software, delivering better dynamic verification through automated graphical test bench generation and easy viewing in the Project Navigator processes window
• More capacity and faster performance than MXE-II
• Support for system Verilog and Verilog PLI/VPI
• Excellent debug environment
• Waveform management tools
• Customizable user interface
• Batch-mode simulation
• HDL editor
• Source code debugging
• Verilog-2001 or VHDL-93 support (single language product)
• The MXE-III Starter version offers 50% faster HDL simulation and 20 times more design capacity than MXE-II
• Upgrade path to more powerful simulators such as ModelSim PE and SE

ISE SIM 8.1i features include:

• Mixed-language Verilog 2001 and VHDL-93 design support
• Simple user interface
• Export to XPower for easier device power estimation
• Integrated wave editor for test bench creation
• Design hierarchy, waveform, and console views
• Source-level debugging
• Command-line console with TCL interface
• Does not require FlexLM licensing
• “Generate Expected Results” process generates expected design output behavior based on input stimulus

Easier Verification of Hierarchical Designs
A capability in the ISE Foundation toolset called KEEP_HIERARCHY makes it much easier and faster to debug hierarchical designs. This design flow not only decreases the time it takes to run timing simulation, but also addresses the bigger problem of finding and resolving problems during the debugging stage.

The idea is to maintain the hierarchy of selected sub-modules when the design goes through the synthesis and implementation flow and then verify these submodules in timing simulation before the entire design is assembled and verified. Each sub-module can be written out as a separate netlist and verified both in RTL simulation as well as in timing simulation with a separate associated SDF file. Because each sub-module for a timing netlist looks the same as the RTL version (with the same top-level port names), the same test benches can be used in timing simulation that were used in RTL simulation with little or no additional work.

Analysis of this methodology on typical Virtex™-4 designs has shown that both the simulation run times as well as the memory requirements required for simulation were considerably reduced. See the “Design Hierarchy and Simulation” section in the ISE 8.1i Synthesis and Verification Design Guide for more information.

Faster Simulator Performance for Xilinx Devices
Xilinx and its partners understand that shorter simulation runtime is a never-ending goal. Cadence NC-Sim v5.5, with its hard-coded Xilinx library primitives, and Mentor ModelSim SE 6.1, with ‘vopt’, have improved simulation runtime.

Advanced Verification Methodologies

Assertion-Based Verification
Assertion-based verification (ABV) is a blend of assertions, functional coverage, and formal model checking technologies applicable to both ASIC and Xilinx FPGA designs. Assertions are explicit expressions of design intent, capturing what a circuit structure should or should not do. By embedding assertions in a design and having them monitor design activities, assertions improve the observability of the design. For more information on ABV for Xilinx FPGAs, see “Early Defect Discovery with Assertion-Based Verification Accelerates Design Closure,” also in this issue of the Xcell Journal.

Equivalency Checking
EC is a static verification technology that uses formal techniques to determine if two versions of the same design, at different stages of development, are functionally equivalent. This offers 10 to 100 times faster verification time and 100% functional coverage, with no test vectors required. It is also able to check for any tool-induced bugs. EC can eliminate long simulation runtimes when doing functional checks, as code is modified to meet your timing goals.

To use the EC flow for Xilinx devices:

1. Download the EC libraries at www.xilinx.com/ise/partner_libraries.
2. Set up the synthesis and implementation tools to generate “formally verifiable” netlists by turning off optimizations such as constant registers removal, register duplication, register merging, and disable re-timing.
   • In Synplify Pro, use the following variables to enable EC and write out the automated setup file, <deign>.vif (text): set_option -verification_mode 1 set_option -write_vif 1
   • In DC FPGA, include set_fpga_default -formality to enable EC and write out the automated setup file, .svf (encrypted).
   • For ISE enable ‘netgen -ecb’ to ensure that the .svf file includes a listing of ISE optimized constant registers.
3. Output an EC-friendly Verilog netlist from CoreGen. The netlist is used as a functional model for each instantiated CoreGen IP to successfully verify CoreGen blocks for the post synthesis to post-PAR check.

• Use CoreGen to instantiate large block RAMs in the RTL (Figure 5)
• Turn off re-timing in the synthesis tool
• Isolate wide multipliers to a separate hierarchy and then black box it
• Replace old instantiated components when targeting the RTL to a new architecture

• Synplicity Synplify Pro V8.0+ synthesis with Conformal V5.0+
• Synplicity Synplify Pro V8.0+ synthesis with eCheck V4.3+
• Synopsys DC FPGA V2005.03+ with Formality V2005.03+

• Improved timing accuracy
• Better integrated and easier-to-use tools
• Hierarchical design support
• Faster simulator performance
• New methodologies

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