The FPGA-based embedded system design flow provides many benefits to system developers, as well as new challenges. Chief among the benefits are accelerated design flows that allow you to move quickly from the design and testing cycles to marketing and selling. With this accelerated flow, it is more important than ever that the hardware and software designs are in sync throughout the entire engineering design cycle.

Accelerated Technology, A Mentor Graphics Division, has developed a version of its Nucleus embedded software suite that integrates with the Xilinx® Embedded Development Kit (EDK). This provides a tight integration of software systems in the FPGA embedded systems design flow. EDK is based on a data-driven code base that makes it extensible and open. By leveraging this functionality, Nucleus software is able to achieve a level of integration into the FPGA-based embedded system design flow that was previously not possible.

The Nucleus embedded software suite for Xilinx FPGA system design includes a complete tool offering and target software platform, including high-level modeling with xtUML and advanced target software debugging with the Eclipse-based Nucleus EDGE environment.

Auto Configuration with MLD
The underlying technology of the Xilinx approach is microprocessor library definition (MLD). This technology allows for automatic kernel configurations and the generation of board support packages (BSPs). This unique and straightforward approach allows the Nucleus embedded software suite to configure to FPGA system designs created in EDK. This eliminates the need to re-port the software system to the new memory map and peripherals for every hardware design cycle.

The Data-Driven Approach
EDK uses two main data repositories to store information on hardware- and software-related settings. All hardware-related settings are stored in the MHS (microprocessor hardware specification) file, while software-related settings are stored in the MSS (microprocessor software specification) file. These files provide a database that other tools in the Xilinx system can access for any given project.

The data-generation component, as defined in a TCL file, takes hardware details from the MHS data file and custom information from the MLD file and decides which files to generate and what parameters to customize. The Nucleus-specific functions of the TCL file encapsulate the entire algorithm, generating consistent information used by the Nucleus kernel to support a wide range of hardware IP configurations (see Figure 1).

The elements of the Nucleus PLUS realtime kernel modified by the data generation file include:

• The number and type of peripherals used
• Memory map information
• Locations of memory-mapped device registers
• Timer configurations
• Interrupt controller configurations

Core Generation
Xilinx currently offers two processor choices for implementation in their FPGAs: the PowerPC™ 405 hard-core processor and the MicroBlaze™ soft-core processor. The Nucleus embedded software suite currently works with both options. Once you have selected your processor and configured your system inside EDK, enabling Nucleus is as simple as a drop-down menu selection.

Configuring Nucleus and BSP Generation
After you have generated your basic system design and core selection in EDK, you are ready to implement the Nucleus embedded software suite. As Figure 2 illustrates, we leveraged Xilinx MLD technology to add this functionality to EDK.

Once you have configured Nucleus to fit your system requirements, generating the corresponding BSP is straightforward. Simply choose the “Generate Libraries and BSPs” from the Tools menu option in EDK. This will build the correct libraries and any associated applications that the Nucleus embedded suite requires in order to run on your newly designed system.

System Debugging with Nucleus EDGE
You now have your hardware defined and the Nucleus PLUS kernel configured to run on your new platform. But what about software development? Where do we go from here?

Introduction to Nucleus EDGE Accelerated Technology offers the Eclipse-based Nucleus EDGE development environment, a complete development environment that supports JTAG debugging of both PowerPC and MicroBlaze processors. Nucleus EDGE extends the Eclipse platform for multicore, multi-process, multi-thread debugging. It can be installed as a stand-alone or into Platform Studio SDK to provide advanced debugging and project management capabilities.

Nucleus EDGE is state-of-the-art debugging technology that includes features such as:

• Full multi-core/multi-process/multithread debugging, with support for synchronous operation on multiple cores simultaneously
• Advanced C-like scripting language (codelets)
• Data-driven target/core/peripheral descriptions (XML)
• Support for freeze-mode/run-mode debugging (OS- and hardwaredependent)
• Pluggable kernel awareness (data-driven)
• Pluggable connection devices
• Pluggable core support
• Pluggable real-time trace support
• Pluggable profiling engine

BSPs
When targeting traditional processors with Nucleus EDGE, you are responsible for creating and maintaining BSPs that the debugger and project manager use. One advantage of Nucleus software integration with EDK is that BSPs are generated automatically, making maintenance painless. When you finish your hardware design and generate the BSP, the Nucleus EDGE BSP is also generated. This BSP is then used to determine appropriate tool defaults when creating applications, or knowing the layout of memory and peripherals when debugging.

Getting Started with Project Management
Nucleus EDGE provides a powerful user interface to change compiler settings for a given project, or optionally override them for a particular file. You are free to type in the command-line arguments if you know them, or you can peruse the options using a tree, which contains information about the command and allowable settings for it. It is nice not to have to wade through obscure compiler documentation to find the setting you need and its syntax (Figure 3).

Editing and Building
Nucleus EDGE provides a full-featured context-sensitive editor for C/C++ as well as assembly. The editor provides the following features:

• Configurable syntax highlighting (you can change the colors)
• Outliner that aids in navigation for your active source file
• Right-click navigation for declaration/definition of function calls
• During debugging, hovering over variables displays their current value; additionally, you can define your own script functions to render tool tips for your application data types
• Code completion for both functions and macros

Debugging PowerPC and MicroBlaze Processors
For Nucleus PLUS kernel applications, Nucleus EDGE can support run-mode debugging – the debug of individual tasks while the rest of the system continues to run. To accomplish this, it can use a serial port, Ethernet connection, or even the Xilinx JTAG UART.

For MicroBlaze processors, Nucleus EDGE currently supports debugging through XMD (Xilinx Microprocessor Debugger). For PowerPC, connection options include XMD, or, for PowerPC designs in which you have instantiated a dedicated JTAG scan chain, third-party JTAG devices such as Abatron’s BDI2000 and MacCraigor Systems On Chip Demon family of connections.

Platform Debugging (Hardware/Software Co-Debugging)
One useful feature gained from connecting through XMD is that you can leverage ChipScope™ Pro hardware debugging features simultaneously while you debug your software using Nucleus EDGE. In the ChipScope Pro GUI, you get a logic analyzer view of signals inside your core. You can then configure the ChipScope Pro analyzer to halt the processor when the state of a certain peripheral changes, for example. When this occurs, Nucleus EDGE synchronizes, and you see the exact state of your software when the event occurred.

Debugging
Nucleus EDGE contains many special features for embedded debugging. The register view, for example, shows groups of native processor registers as well as memory-mapped peripherals. Those bits in the register that are set are highlighted in an optional graphical control. Bit-mapped registers show the bits set, and allow you to control them individually. In Figure 5, you can see that “Exception Enable” is bit 6 in the MSR (the bold box around the bit), and that the bit is not currently set (the blue background). Gone are the days of getting out your calculator to do binary conversions and counting bits to figure out if a bit is set. Figure 5 also shows how values that changed from the last step are color-coded (red).

Breakpoints
One other compelling feature that Nucleus EDGE offers above and beyond the capabilities of Platform Studio SDK is built-in integration with hardware breakpoints. As you may know, you can locate as many as eight program counter hardware breakpoints (used for stepping), as well as four read watch points and four write watch points in a given MicroBlaze design. Nucleus EDGE offers a completely integrated and graphical method to set both types of breakpoints. Also, the Nucleus EDGE debug engine is able to use the hardware breakpoints seamlessly to enable stepping in ROM.

Multi-Core Debugging
The number of MicroBlaze cores that can be placed in a design is only limited by the size of the FPGA. However, the MicroBlaze debug module can support debugging of as many as eight MicroBlaze cores simultaneously. The Nucleus EDGE user interface and debug engine have the ability to create “synchronization groups” of different cores. When one of these cores stops, all of the cores in the group are stopped.

Although Xilinx does not currently ship an IP block that supports configuration of synchronous control of multiple cores, it is a relatively trivial matter to implement it yourself – after all, you have an FPGA. Simply tie together a memory-mapped register with some MUX logic on the MB_HALT pin (that indicates that a core has gone into debugging state) as well as the DBG_STOP pin (that can force a core into debugging state). This way, when one core in a group either hits a breakpoint or has an exception, all of the cores stop. Then, in Nucleus EDGE, you can provide a codelet script that sets this register appropriately.

Codelets/Scripting
Nucleus EDGE contains support for a scripting language that we call “codelets.” The syntax is standard ISO/ANSI C, with a few extensions. Simply put, codelets are scripts that run in the debugger but have full visibility and control over the target.

You can access target registers, memory, and variables, as well as call target functions from within a codelet. You can read and write host files as well as sockets. You can open “channel viewers” in the debugger GUI and execute them through any different expression evaluation. You can call them from the command line, or when hitting a breakpoint, or by typing an expression in the watch window. Codelets are meant to be an enabling technology. They allow you to get inside your hardware in a way that is not otherwise possible. Some things that customers have done with codelets include:

• Board initialization during debug
• Complex conditional breakpoints
• Custom hardware validation/ regression testing
• Virtual console I/O
• “Poor man’s” kernel awareness
• SmartWatch – the ability to define a codelet that is used to “render” a given data type to a string, giving you nice tool tips for your data structures when debugging

• Generic text console I/O (standard I/O with the app)
• VT-100 compatible console I/O (supports escape sequences)
• Strip chart recorder that allows you to plot any value over time in real time
• Windows Media Player streaming plug-in (plays MP3s, MPEG video) (on Windows hosts only)
• Binary data viewer (like the memory view, in effect a “protocol analyzer”)

Kernel Awareness
Nucleus EDGE kernel awareness gives you the ability to see a snapshot of the state of your system, as well as providing the ability to set thread-dependent breakpoints. We currently provide out-of-the-box kernel awareness for the Nucleus PLUS kernel. However, Nucleus EDGE also gives you the ability to configure your own kernel awareness. This can be done for a third-party RTOS, an inhouse kernel, or no RTOS at all.

Nucleus EDGE provides a data-driven mechanism to describe how it should iterate objects of a given type and display their attributes. They do not even have to be software objects – they could be anything that is memory-mapped (Figure 6).

Conclusion
Configurable cores are the future of embedded development. With the combination of auto configuration of Nucleus target software and advanced debugging with Nucleus EDGE, Accelerated Technology has bridged long-standing gaps in integrated system design. By supporting both PowerPC- and MicroBlaze-based FPGA systems, Accelerated Technology distinguishes itself from the competition and provides unparalleled software tools and support for FPGA system designers.

For more information, evaluations, and updates to these exciting technologies, visit www.acceleratedtechnology.com/xilinx.

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