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DSP algorithmic realization in FPGA
fabric can be easily controlled and
debugged through high-speed Ethernet
communication. This interoperable solution
allows for portability and usage in
other designs. Because of the widespread
use of the standard, the FPGA is capable
of transmitting data at high speeds to a
vast array of external devices.
In the example well present in this
article, a broadcast HTML page is used as
a debugging interface to the FPGA. This
broadcast page can be easily modified
through software to tailor to your debugging
needs. The design is built on a sample
design packaged with the Xilinx®
ML403 Virtex-4 evaluation board, in
which the HTML code is stored locally to
the FPGA. Connecting to the IP address
of the Ethernet MAC (media access controller)
through a Web browser loads the
HTML file.
Ethernet Basics
The first Ethernet standard was produced
in 1985. Ethernet fits into the Open
Standards Interface model of the
International Standards Organization, as
illustrated in Figure 1. Several LAN technologies
are in use today, but Ethernet is
by far the most popular technology for
departmental networks. The vast majority
of computer vendors provide equipment
with Ethernet attachments, making it possible
to link all manner of computers with
an Ethernet LAN.
Transmitted data is encapsulated in a
so-called Ethernet frame, which has
defined fields for data and other information
such that the data gets to its destination
and the destination computer is able
to discern whether the data it receives is
valid. The frame format defines Ethernet
and is illustrated in Figure 2. Frame sizes
vary from 64 to 1518 bytes, and can be up
to 1522 bytes when VLAN (virtual bridged
local area network) is tagged.
As noted in Figure 2, the source and
destination address of the transmitted data
is encapsulated within the frame. The other
fields consist of:
- The preamble, which is a repeating
pattern of 1010 needed for some PHYs
- Start-of-frame delimiter (SFD), which
marks the byte boundary for the MAC
- Type/length of frame
- Data
- Pad, which is only necessary
to extend the frame to 64
bytes
- Checksum, which implements
a cyclic-redundancy
check (CRC) to determine if
the frame is sent in error
- Idle, which occurs between
frames and must be at least
96 bit times
Ethernet frame transmission is controlled
by the MAC layer. The MAC handles
data encapsulation from the upper
layers, frame transmission and reception,
data decapsulation, and delivery to upper
layers. The MAC operates independently
of the physical layer employed and thus
does not need to know the speed of the
physical layer (as shown in Figure 3).
The Virtex-4 series offers two embedded
Ethernet MACs. In this way, C-code
software implementation through the
PowerPC processor can be used to tailor
the MAC to the particular application. You
are thus encapsulated from the lower layers
of the MAC.
The Xilinx Ethernet Register Interface
The Ethernet capability of a Xilinx FPGA
allows for possibilities such as broadcasting
captured data from the FPGA to an
HTML-based website. In this manner, data
can be sent to and retrieved from the
FPGA through user I/O to the HTML
GUI. The HTML page we used in building
our project is shown in Figure 4.
A register interface is critical in the
debugging of a design. It allows you to trigger
events, obtain the status of intermediate
results, and dump the values stored in
block RAM. The latter is especially useful
for processing and verifying a partial piece
of an algorithm. As an example, an FPGA
with an ADC feeding into it can serve as a
sampler through a register dump of stored
ADC sampled data in block RAM.
The contents of block RAM data can
be accessed through a simple register read/write procedure. To read, we select an
SRAM block by writing the block number
in Register 1, and write the SRAM address
to Registers 2 and 3. After the completion
of register writing for Register 6, the
SRAM contents corresponding to the
SRAM address written in the SRAM block
selected are available for read out through
Registers 4, 5, and 6.
To write a register, we select an SRAM
block by writing the block number in
Register 1, and write the SRAM address to
Registers 2 and 3. Then we fill the SRAM
contents we want to write into Registers 4,
5, and 6. After the completion of register
writing for Register 6, SRAM contents will
changed to new value.
The schematic shown in Figure 5 shows
a single 8-bit register and the signals needed
to control it. A select bus allows for
multiple registers based on the size of the
select bus. The write_d0 signal allows
the register to be written to. When reading
a register, its contents appear on the
REGOUT(7:0) output, and this output is
fed back to the HTML page during a register
read. The alternative register output is
used to act as control signals, sample input
to block RAMs, or whatever the situation
may call for. Well provide a detailed
description of the transmission of data
from the register to the HTML debugging
page in the next section.
Implementation of the
Ethernet Register Interface
The Xilinx EMAC interface we used supports
the IEEE Std. 802.3 media independent
interface (MII) to industry-standard
physical layer (PHY) devices and communicates
to the PowerPC processor
through an IBM on-chip
peripheral bus (OPB) interface.
The EMAC comprises
two IP blocks as shown in
Figure 6. The IP interface
(IPIF) block is a subset of the
OPB bus interface features
chosen from the full set of
IPIF features.
The proposed EDK design
to implement the register interface
through Ethernet uses a
general-purpose input/output
(GPIO) core for the processor
local bus (PLB) bus. The
GPIO is a 32-bit peripheral
that attaches to the PLB. We
used this GPIO capability to
communicate between the
PowerPC C-software implementation
and the register
interface linked to the DSP
algorithmic implementation
using dedicated logic. Figure 7
illustrates the block diagram for
the Ethernet register interface.
The Xilinx EDK
PowerPC design was easily
integrated into ISE design
tools to access DSP algorithmic
implementation (the
non-software portion of the
design implemented in dedicated
logic). This was
achieved by exporting the
design to ISE software and
encapsulating the logic to
communicate to the PowerPC inside a
schematic block, as shown in Figure 6.
The GPIO bus was used to feed input
and output to the processor, as different
bus lines served different purposes. At a
higher level, this schematic block was
packaged with a state-machine interface
to achieve the register communication to
the FPGA, as illustrated in Figure 5.
Xilinx ML403 Board: Test
Platform for the Interface
At first, the task of employing Ethernet as a
means of communication between the
FPGA and the outside world seems pretty
daunting. This is not the case, as Xilinx provides
a reference design from which to build
your own custom design. Xilinx also offers a
tutorial for those not familiar with implementing
processor designs using EDK.
The ML403 Embedded Processor
Reference System contains a combination
of known working hardware and software
elements. The reference system demonstrates
a system utilizing the PLB, OPB,
device control register (DCR) bus, and
the PowerPC 405 or MicroBlaze
processor core. The design operates under
the EDK suite of tools, which yields a
graphical tool framework for designing
embedded hardware and software. Each
of the pieces of the system can
be separately activated as a
stand-alone project.
The proposed Ethernet register
interface was built from the
Webserver project, which comes
as part of the ML403 reference
system. The Webserver project
implements an Ethernet MAC
through an IBM OPB, built-in
for interfacing with the PowerPC
405. This core supports
10BASE-T- and 100BASETX/FX-compliant PHYs in fullor
half-duplex mode.
The reference design serves
as a good starting point to get
you up and running with a
design. The groundwork is laid
out for you, allowing for additional
modifications and
enhancements.
Conclusion
What better way to transmit
data from the FPGA to an auxiliary
device, be it a web page
or server, than Ethernet?
Regarded as one of the most
interoperable communication
standards, Ethernet allows you
to achieve high-speed data
transmission with a widely
employed standard.
Virtex-4 devices offer two
embedded Ethernet MAC
cores, and when combined
with the design environment
ease of EDK, an application for data
transmission can be achieved with relative
ease through C-code software implementation.
The capabilities of such a system
allow for FPGA algorithmic debugging
and trigger, as well as SRAM fill and read
at speeds as high as 1 Gbps, providing
control and debugging of dedicated logic
DSP algorithmic realizations.
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