Managing your system power within budget is essential to maintain reliability in your system. Failure to do so may cause components to break down and reduce reliability.

The semiconductor industry’s rapid move toward 90 nm silicon processes benefits the performance and cost aspects, but places enormous pressure on power budgets. As transistor sizes decrease, leakage current (and hence static power) increases exponentially. Dynamic power also increases, with increasing system speed and larger design density, but in a more linear fashion.

Today, many designs have 50/50 static and dynamic power dissipation. According to International Technology Roadmap for Semiconductors (ITRS) projections, static power is increasing exponentially at every process node; thus, innovative process technologies are imperative.

With the adoption of FPGAs in more markets and systems every year, driven by increasing performance/density and decreasing price, FPGA power consumption within the entire system is becoming critical. Leading FPGA vendors are already adopting new techniques to mitigate static and dynamic power consumption.

Power Consumption Considerations
The amount of power being consumed in the system is very important, and FPGAs (often used for system integration functions) make up the majority of power consumed in these systems. A given system or individual components usually have a power budget, which falls into two major areas. The first area is a simple practical one, which is to accommodate the power capacity of the supplies used in a design to meet system power needs. The second area is about thermal concerns, which you need to understand to keep the system working within its various components’ temperature specifications. To this end, it is important to know where power consumption comes from in the FPGAs you choose and how you can optimize it.

Working Within a Power Budget
As mentioned, the power budget arises because of power consumption and thermal concerns. Here is a typical example: a board has a power budget of 20W with a normal operating environment of 10°C to 40°C. Under conditions of a failed fan(s), ambient air above certain components may rise above 70°C. Many components’ manufacturers have operating conditions that range as high as 85°C in junction temperature (for commercial grade) and 100°C for industrial grade parts. Using Xilinx® ISE™ XPower or Web-based power estimation tools, you can see where power consumption will fall and if you will need to optimize your FPGA’s power consumption. It is also important to learn what consumes power in the FPGA and what methods of design optimization may be available to help reduce consumed power.

Where is Power Consumed in the FPGA?
There are two primary areas of power consumption in FPGAs. Static power comes from transistor leakage; dynamic power comes from voltage swing, toggle rate, and capacitance. Both are important factors in meeting a power budget and power optimization. It is therefore important to know what each factor is and how it varies with different operating conditions.

Static Power
Static power is power consumed by transistors due to leakage. This leakage is now significant for 90 nm devices. To get higher performance from the transistor, you need to lower the voltage threshold, (VT) of the transistor, which also increases leakage.

Leakage of the 90 nm transistors varies strongly with process: the VT of the transistors varies because of doping, and the gate length varies because of lithography. This can produce strong changes in transistor speed and leakage. Reduced VT or gate length both increase leakage and speed, while the converse is also true. The variation in leakage and static power is about 2 to 1 between worst-case and typical process.

Leakage and static power are also influenced strongly by core voltage, V_CCINT, with variations that go approximately as the square and cube, respectively, of V_CCINT. Static power shows a ~15% increase, with only a 5% increase in V_CCINT. Leakage is very strongly influenced by junction (or die) temperature, T_J.

Because each of these factors – process, voltage, and temperature – have a strong effect on leakage and static power of the FPGA, it is important for you to understand them and how they might influence total power consumption of the FPGA or ASIC. Gate-to-substrate leakage is also part of total leakage, but is not highly temperature-dependent.

Figure 1 shows the variation in transistor leakage and static power in 90 nm FPGAs due to process, voltage, and temperature.

Seeing the increasing transistor leakage when moving toward a high-performance 90 nm FPGA, Xilinx IC designers chose to adopt the use of a third gate-oxide thickness in the transistors of the newest Xilinx Virtex™-4 FPGAs. In previous FPGAs and ASICs, only two oxide (dual-oxide) thicknesses exist: a thin oxide for core transistors and a thick oxide for I/O transistors. The use of a third middle thickness of oxide (triple-oxide) and higher VT in a portion of the transistors of Virtex-4 FPGAs allows for a dramatic reduction in overall leakage and static power compared to other competitive FPGAs, which do not use triple oxide. So although variations with process, voltage, and temperature are still present, the absolute leakage in Virtex-4 FPGAs is about one-third that of competing high-performance 90 nm FPGAs.

Dynamic Power
Dynamic power is power consumed by transistors and traces that are toggling. The effect, simply put, is from changing an internal voltage from a logic “0” to a logic “1” (or vice versa) and charging a capacitance to that voltage. The more often this is done, the more power consumed. In the FPGA, transistors are used for logic and programmable interconnects between metal traces. The capacitance that we are talking about is transistor parasitic capacitance and metal interconnect capacitance.

The formula for dynamic power is:

PDYNAMIC = nCV²f

All nodes in the FPGA consume power through a combination of charging transistor parasitic capacitance and metal interconnect capacitance. The latter depends on the length of routes in the FPGA, while net node capacitance is determined by the number of transistors that are switching. Tighter logic packing will reduce the number of switching transistors and minimize routing lengths, which will reduce dynamic power.

Figure 2 shows the variation of dynamic power with voltage swing and core voltage, VCCINT. Process and temperature cause little variation in dynamic power. Taken together, their effect is less than 5-10%.

Lowering Design Power by Changing the FPGA Environment
To optimize the power consumption of a given design, there are certain things that you can do independent of the design contained in the FPGA. Knowing the environment is therefore important.

Temperature
Controlling temperature can help reduce static power. A reduction in junction temperature from 100 °C to 85 °C will reduce static power by ~ 20% (as shown earlier in Figure 2). Even though the static power of the Virtex-4 FPGA is already low compared to other 90 nm FPGAs, reducing it by another 20% is valuable, since in some designs static power of the FPGA represents a sizeable portion (30-40%) of the total power budget. The reduction in junction temperature can be achieved by increased airflow and larger heat sinks, which will transfer heat away from the FPGA, reducing junction temperature. The reduction in junction temperature also has the added benefit of increasing reliability.

Voltage
Keeping core voltage at or below nominal will reduce static and dynamic power. Static and dynamic power consumed at the core voltage, VCCINT, is often the largest power consumer in the FPGA. FPGAs are usually specified to be able to run and meet performance with power supply voltage within +/- 5% of nominal. Figure 2 shows that a +/- 5% variation in VCCINT causes a ±15% and ±10% variation in static and dynamic power, respectively. To the extent that the VCCINT power supply can be specified more tightly, you can also set it to be at or even slightly below nominal rather than being able to have a worst case that is 5% above nominal.

Lowering Design Power by Changing the Design
To make FPGA design-related tradeoffs in power consumption, it is important to know where you should start. Xilinx has several design tools that can help you get an early or detailed estimate of design power consumption.

Based on your estimates of design size (logic and flip-flops), operating frequency, toggle rates, embedded block utilization, and environment conditions such as temperature, the Xilinx Web Power tool shown in Figure 3 allows initial estimates to be made on the power consumption of a given design. It does not rely on detailed information about the design such as exact routing, placement, and utilization.

The XPower tool included with all configurations of ISE software is a detailed power analysis program that allows you to input stimulus vectors for the design. Along with the information from the actual routed and placed design, the tool calculates power consumption much more accurately, as shown in Figure 4.

FPGA Design
Techniques to Reduce Power Several design-specific techniques can also reduce power consumption. These include constraining logic to a small area where possible, setting synthesis flags to minimize area, and minimizing layers of logic. Pipelining is also a good technique because it allows a higher timing constraint to be set, which allows reduction of capacitance and thus dynamic power reduction.

Setting Placement and Timing Constraints
Floorplanning the design properly reduces dynamic power. ISE Floorplanner allows you to create placement constraints. A more sophisticated floorplanning tool from Xilinx called the PlanAhead™ design tool allows you to observe hierarchy in a design and group sets of related logic into small areas. Using the placement and grouping constraints reduces the physical area, allowing you to achieve higher performance while minimizing routing capacitance and reducing dynamic power consumption.

Other techniques include constraining timing in a design. Synthesis tools as well as ISE routing and placement tools allow you to input timing constraints. If you raise the target timing constraint – especially the clock target – the router will try harder to meet it through more aggressive placement and routing efforts. The net effect is to minimize routes, which reduces routing power.

Other Partial Shutdown or Reprogramming Methods
Other commonly used design techniques can help reduce dynamic power consumption. One of these techniques is to use clock multiplexing. This entails turning off sections of the FPGA. A hardware feature in the Virtex-4 FPGA and its predecessors is a clock gating block, which allows a smooth way to turn off or on a global clock net. Better than clock enables on flip-flops, this method allows the entire large toggling clock net to be gated off, which saves power on the net and on the flip-flops.

Some types of designs, especially those used in battery-type applications, only need to consume power at certain times. In these applications, you can turn off clocks and lower the core voltage to the minimum level that still allows FPGA data retention. In the Virtex-4 device, this is 0.9V. At this level, static power is reduced by greater than 60% when compared with the nominal 1.2V level.

A way to shrink the FPGA size required for a given set of tasks is to use the dynamic reconfigurability port, or DRP, which is available in Virtex-4 and other Xilinx FPGAs. If there are several functions that don’t need to coexist, this port allows reloading only a portion of the FPGA. In doing so, you can choose a much smaller FPGA, which reduces static power.

Use of Embedded Blocks
Another method of reducing power consumption is through the use of embedded blocks. Although it is more work in some cases to instantiate special blocks, Virtex-4 FPGAs have a number of pieces of hard IP, which are essentially ASIC gates. Some of these functions are in fact automatically synthesized by some of the modern synthesis tools. These new blocks have between 5x and 20x lower power than programmable logic and programmable interconnect implementations. The embedded blocks reduce static power by not having extra transistors (as in programmable logic) and by not using programmable interconnect transistors. They reduce dynamic power by using only metal interconnects versus metal and programmable interconnects; reducing trace lengths; reducing extra node capacitance because of lack of pass transistors; and minimizing layers of logic.

Some of these blocks include the following:

• PowerPC™ – embedded high-performance processor
• DSP – XtremeDSP™ slice, a highperformance sophisticated multifunction arithmetic and logic block
• SSIO – New ChipSync™ block available in every I/O pin reduces logic cell counts for source-synchronous I/O designs
• Embedded Ethernet MAC(s) – no need to use logic and interconnect for MAC functions
• FIFO – SmartRAM memory includes built-in FIFO controllers
• SRL16 – Allows multiple cascade flipflops to be used without programmable interconnects

Future releases of ISE software will offer more power-optimization enhancements, including power-optimized synthesis and power-optimized placement.

Conclusion
It is very important to know the system power budget and operating environment. Understanding where various forms of power consumption come from allows you to adjust the FPGA environment and design characteristics to minimize power consumption and successfully meet a given power budget.

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