The Xilinx® PlanAhead™ hierarchical design and analysis environment can be used in conjunction with Xilinx ISE™ tools to improve design performance and possibly enable incremental design and IP reuse. Several customers have benefited from the unique capabilities that PlanAhead software provides. In this article, we’ll describe how one Xilinx customer, Anchor Bay Technologies of Campbell, California, was able to successfully utilize PlanAhead design tools.

A Custom Chip in Three Months
Anchor Bay Technologies specializes in designing and developing video processing system- and silicon-based solutions for scaling, de-interlacing, and noise reduction.

Recently, Denon Electronics Company required a very high-performance scaling chip for their high-end DVD players to take standard-definition 480P video from the MPEG decoder and scale it to 1080P resolution for large display applications. Anchor Bay had developed several scaling chips, but Denon required a custom design to fit their specific application. In particular, they wanted multiple video output streams, multiple video formats and resolutions, and a custom I2C interface to the chip.

Faced with a very short development cycle and unable to turn an ASIC in this timeframe, Anchor Bay decided to develop a custom solution based on Xilinx Spartan™-3 FPGA technology. They had only three months to get the chip designed and tested for initial sampling.

Anchor Bay used ISE Foundation™ design tools to perform basic design and simulation. Because Denon required the lowest cost solution, they tried to fit the design into the smallest Spartan-3 device that had enough resources. But because of the aggressive performance requirements, achieving timing closure was close to impossible using conventional ISE floorplanning and place and route (PAR). The design involved four different clock domains – the highest frequency at 148 MHz. The design was using more than 80% of the Spartan-3 XC3S1000FT256-5 part, 100% of the multipliers and clock buffers, and 60% of the RAM blocks.

This heavy utilization made timing closure very difficult. There was no way to guide the tools adequately to close on the critical paths. In addition, the tools did not clearly point out routing bottlenecks that were hindering timing closure.

After several attempts, Anchor Bay decided to explore the PlanAhead design tool from Xilinx to see if it could provide a solution. Their FAE support team was very responsive. They obtained an evaluation copy of PlanAhead software and quickly studied the tutorial before the FAEs came to their offices and walked them through the methodologies.

Problem Solved
PlanAhead design tools allowed Anchor Bay to quickly pinpoint the resource bottlenecks and the relationship between timing paths and placement. They were able to attempt several “what-if ” scenarios to better open routing channels and group critical timing paths. Taking the results from the ISE timing analyzer and feeding them back into the floorplanning tool was invaluable. Also, the ability to view the schematic allowed them to change the logic where necessary to reduce the critical paths. They found that providing a simple floorplan was enough of a seed to allow the PAR tool to meet their timing needs.

They did not need to use PlanAhead software to heavily constrain the PAR tool, but only concentrated on the critical paths and congested areas. After more than two weeks of trying without success, they accomplished what they needed in two days using PlanAhead design tools.

Anchor Bay is continually pushing the limits of the FPGA devices in their systems. This allows them to not only sell ASIC solutions, but also to develop custom, cost-effective silicon solutions based on FPGA technologies.

Another Customer Example
Like Anchor Bay, a number of other customers have benefited from PlanAhead’s advanced capabilities. For one such customer, the objective was to reduce PAR runtime and meet timing. To achieve this, they used PlanAhead software to quickly analyze the design, find the bottlenecks, and create the necessary physical constraints.

PlanAhead’s ability to place individual instances at specific locations and to constrain multiple instances to desired area groups was very useful in this process. Figure 1 shows a PlanAhead view showing the critical paths not meeting timing.

Figure 2 shows how PlanAhead design tools were used to create specific LOC constraints. The final floorplan created using PlanAhead software is shown in Figure 3, while the results achieved through use of PlanAhead design tools are recorded in Table 1.

Conclusion
A growing number of customers are using PlanAhead software to help them tackle tough design problems. In doing so, they have increased their productivity while achieving and maintaining their design requirements. These benefits include:

• Reaching and maintaining performance goals
• Quicker incremental design changes
• Faster PAR time
• Fewer design iterations
• Tighter utilization control
• IP reuse

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