Every customer I know is feeling the pressure to cut design costs. Project budgets continue to shrink, while the pressure to be first to market forces shorter design cycles and fewer engineers per project. But did you know that there’s a wealth of technology meant to help you do just that – shorten your design cycle, solve your design bottlenecks, and lower your overall design costs? These features are already built into Xilinx® Integrated Software Environment (ISE™) software.

Higher Performance – Faster Project Completion
The measured 70% performance advantage of ISE design tools (versus competing PLD tools) applies beyond bleeding-edge, high-performance digital projects. Lower speed projects also benefit from this performance advantage by allowing you to hit your performance targets early in the design cycle.

You spend less time tweaking and iterating through the implementation phase. ISE place and route tools also help you ensure efficient implementation. The place and route tools and reports can offer interactive suggestions about how you can change your HDL code. These suggestions help make more efficient use of FPGA resources and can save overall design space.

More high-performance technology is packed directly into ISE design tools than any other PLD design offering, including core capabilities like timing-driven mapping, global optimization, design re-timing, and FPGA physical synthesis. Together, this ProActive Timing Closure technology leads to higher overall design performance, and more technology focused on helping you achieve timing closure.

The timing-driven map option helps deliver better utilization to your target Xilinx FPGA device, particularly if the device is already more than 90% utilized (the point at which most PLD users have to consider moving up to the next higher density and more costly device). Timing-driven map combines placement with logic slice packing to improve placement quality for “unrelated logic.”

Using timing-driven map offers you the potential to stay in your chosen device – even if utilization is pushing 90% or higher – when competing tools would have forced the design into a larger and more expensive device.

Cutting Through Design-Flow Bottlenecks
ISE design tools focus on solving the problems that plague traditional PLD designs and deliver new tools and technology to speed you through the design flow faster, saving time and money. The ISE 7.1i version includes a host of new tools – including Technology Viewer, message filtering, design summary, ISE Simulator, and ModelSim Xilinx Edition-III – all focused on “ease-of-design” to get you through to project completion faster.

New ISE 7.1i Tools and Technologies
The Technology Viewer lets you view your post-synthesis HDL-based design at the block level in a schematic-like display. It is built on the same graphic interface as RTL Viewer, so there are no new commands or menus to learn. Full hierarchy is represented, so you can easily push down or pop up through your design, highlighting and identifying critical elements by pin, net, or instance name. The Technology Viewer – combined with the RTL Viewer, ISE Floorplanner, and FPGA Editor – bring you more ways to visualize your design and to see and control exactly how the implementation phase is completing your design, helping avoid time-consuming problems and re-implementation steps.

ISE 7.1i software includes a new design summary view that takes the most commonly sought-after design information and places it in one easy-to-use automated display, eliminating the need to search through multiple tool reports and outputs to find exactly what you need. The design summary also contains a list of hyperlinked detailed implementation reports. You can easily jump to more detailed information. The design summary saves design time by delivering the core up-todate design information. The new message filtering capability lets you select the report information that you deem non-critical to your design and suppress it from future reports. Message filtering delivers more streamlined and pertinent report information, and allows you to quickly see the data necessary to your project, making debug and verification quicker and easier.

ISE and ChipScope™ Pro 7.1i tools offer new remote programming and remote debug capabilities. ChipScope Pro and iMPACT programming tools can now run in server/client mode over a TCP/IP connection. You can sit in your office while debugging or programming a board next door in the lab or on the other side of the world. You can share a single board or debug system in the lab with other engineers on your team, or allow help desk personnel to debug a problem remotely at a customer site. Remote programming and debug save you the cost of additional software, and make more efficient use your existing project workstation setup.

Existing Features that Drive Design
The architecture wizards inside ISE design tools are a collection of graphical-based menus and dialog boxes with which you can quickly and easily set the parameters of advanced silicon features. For example, the XtremeDSP™ slice wizard, shown in Figure 1, provides control over the Virtex™-4 XtremeDSP silicon slice technology. This new silicon capability lets you build high-performance DSP filters and custom pre- or post-co-processing DSP algorithms.

The XtremeDSP slice wizard lets you specify accumulator, adder/subtractor, multiplier, or multiplier and adder/accumulator DSP modes. You can graphically set input and output bus data widths, pipelining options, clock enable, and reset pin setups, and then review parameters and output the results as HDL-ready code. Once configured, the architecture wizard writes editable VHDL or Verilog source code that is instantiated directly into your target project. The architecture wizards help reduce the learning curve associated with new silicon releases, and allow beginning FPGA designers to quickly get up to speed programming even the most advanced silicon.

The pin and area constraints editor (PACE) delivered within ISE design tools includes graphical pin and area management that is both powerful and easy to use, as shown in Figure 2. You can drag-and-drop pin assignments onto a graphical map of the device, either by footprint or architectural area. You can group pins logically and by color for easy recognition, specify I/O standards and banks, prohibit I/O locations, and verify legal pin assignments on the fly. PACE can also interface through CSV files, letting the FPGA engineer send pin definitions directly to PCB layout, or read PCB layout information and back-annotate that information to the FPGA design.

PACE can be the starting point of your project, and PACE writes out HDL language template files based on the hierarchy and logic area groups you’ve defined. PACE includes several design rule checks including simultaneous switched output (SSO), which help predict ground bounce problems and account for exact pin delay across your entire design. PACE delivers a wealth of productivity that can help reduce design headaches and lower project costs.

Incremental Design – Shorter Re-Implementation Times
Incremental design, first introduced in ISE 5.1i software nearly three years ago, can slash re-implementation time by as much as 75%. Your design is first floorplanned in PACE or our optional PlanAhead™ software. The design is then completed through the normal implementation cycle. If subsequent modifications are required, incremental design reimplements only the area(s) affected by the design change, leaving the other completed design areas intact and dramatically shortening the design cycle. Incremental design can deliver more design cycles when you need them and shorten your design time.

An Array of Verification Options
Verification is one of the most time-consuming and time-critical phases of the design flow. Incomplete or time-consuming verification strategies can take up more than half of the overall design flow and leave critical logic areas unpredictable. ISE delivers enhancements to the verification flow that help cut the time and cost of verification.

Two HDL Simulation Choices
The ISE Simulator is a new, full-featured HDL simulator delivered with and integrated directly into ISE design tools. It offers the ability to simulate directly from the ISE Project Navigator process window, where test benches, stimulus, and output graphics are generated. ISE Simulator supports VHDL and Verilog, functional and timing simulation, and is licensed through the fast and painless Xilinx software registration ID process – no licensing dongles or Ethernet keys. ,p> ISE 7 software is also the release of the new ModelSim Xilinx Edition-III HDL Simulator. Free to all ISE customers, MXEIII Starter offers 50% faster HDL simulation and 20 times more design capacity than the previous version. For large-density FPGA designs, you can purchase the MXEIII full version, which provides five times the design capacity and 30% faster performance than the MXE-III starter.

ISE design tools preserve design hierarchy throughout the entire design flow, while other solutions are forced to flatten design hierarchy during implementation and verification and then reconstruct that hierarchy for debug. By preserving hierarchy, Xilinx and partner verification tools are able to compile and run your design faster. And because signal names, components, and design instances are preserved throughout the flow, debug is more accurate and cross-probing is easier.

Unrivaled Real-Time Verification
ISE design tools also link directly to our optional, separately purchased ChipScope Pro real-time debug environment. The ChipScope Pro tools insert low-profile logic analyzer, bus analyzer, and virtual I/O software cores during design capture. These cores are then synthesized and implemented into your silicon, allowing you to view:

• Any internal signal within the FPGA
• Embedded processor signals, including the IBM CoreConnect processor local bus or on-chip peripheral bus supporting the IBM PowerPC™ 405 inside
• Embedded processor signals for the MicroBlaze™ soft-processor core

Conclusion
The advanced technology built into ISE 7 software can cut your design and verification times, slash project costs, and offer potentially lower device savings in the long run. All ISE configurations, ChipScope Pro analyzer, PlanAhead software, MXE-III, and ISE Simulator are available for purchase from the Xilinx online store, Xilinx distributors, or by calling (800) 888-FPGA (3742).

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