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ISSUE 52 -- Feature Articles
Virtex-4 Source-Synchronous Interfaces Tool Kit
(3/8/05)
The Virtex-4 ML450 Source-Synchronous Interfaces Tool Kit provides a complete development platform for designing and verifying applications based on the Virtex-4 LX FPGA family.
Using the JTAG Interface as a General-Purpose Communication Port
(3/8/05)
The existing JTAG programming interface in Xilinx FPGAs provides a flexible debug and diagnostic interface.
Applications of the Spartan Family in Flat-Panel Displays
(3/8/05)
A full feature set and low prices make Spartan-3 devices attractive for use within the flat-panel display market.
Leveraging Domain-Specific Product Platforms
(3/8/05)
Reduce risk and development costs by utilizing proven platforms to handle the infrastructure details of your design.
Using DSPs and FPGAs in a Doppler Measurement System
(3/8/05)
DSP applications benefit from a combined Xilinx and TI solution.
CoolRunner-II CPLDs Offer New Features
(3/8/05)
New updates to CoolRunner-II 32- and 64-macrocell CPLDs are now available.
Implementing Bioinformatics Algorithms on Nallatech-Configurable Multi-FPGA Systems
(3/8/05)
A computational acceleration of 200X is impressive, but the future of bioinformatics requires more.
Current Issue 52
Download Entire Issue
Book PDF, 9 MB
Table of Contents
Letter from the Editor
Business Viewpoints
View from the Top
Will the Evolution of Platform FPGAs Mean the End for ASICs and ASSPs?
EasyPath FPGAs Beat ASIC Prices
System Design Challenges
The Virtex-4 Power Play
Deliver Efficient SPI-4.2 Solutions with Virtex-4 FPGAs
Virtex-4 Memory Interfaces
Designing with the Virtex-4 XtremeDSP Slice
Designing For Signal Integrity
Accelerated System Performance with APU-Enhanced Processing
Solving the Signal Integrity Challenge
Using FPGAs in Wireless Base Station Designs
Implementing a Cable Modem Termination System with Virtex-4 FPGAs
Developing Next-Generation Telecommunication Networks
Virtex-4 FPGAs for Software Defined Radio
Virtex-4 FPGAs in Rugged LCD Monitors
Engineering Solutions
ISE 6.3i Software Unleash the Power of Virtex-4 FPGAs
FIFOs Made Easy
Digital Clock Management in Virtex-4 Devices
Virtex-4 Clocking Resources
Alpha Blending Two Data Streams Using a DSP48 DDR Technique
Dynamic Phase Alignment with ChipSync Technology in Virtex-4 FPGAs
Lock Your Designs with the Virtex-4 Security Solution
Dynamic Reconfiguration of Functional Blocks
Designing with the Virtex-4 Embedded Tri-Mode Ethernet MACs
merging Design Methodologies Elicit the Power of Virtex-4 FPGAs
Integrating EDK-Created Embedded Processor Subsystems
Optimizing Virtex-4 High-Performance Designs
Selecting Connectors for Multi-Gigabit Transceiver Designs
Xilinx/Micron Partner to Provide High-Speed Memory Interfaces
Harvesting the Flexibility of Virtex-4 RocketIO Transceivers
Optimize Memory Subsystem Performance with Network FCRAM
General
Using Spartan-3 FPGAs to Implement High-Performance DSP
Engineering Reference
Virtex-4 ML401 Evaluation Platform
Virtex-4 FPGA Source-Synchronous Interfaces Tool Kit
ML461 Advanced Memory Development System
Memec Virtex-4 Board Solutions
Avnet Virtex-4 Evaluation Kits
Nu Horizons Virtex-4 Development Platform
TED DDR2 Memory Evaluation Board
