10 Gigabit Ethernet Media Access Controller (10GEMAC)

产品详细资料

向Xilinx询问该核的问题
Gigabit Ethernet Typical Applications (PDF)
Release Notes (PDF)

文档

10 Gb 以太网媒体访问控制器

支持器件系列

Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
Virtex-5 TXT
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-II Pro

需求

ISE 10.1.3

Designed to the IEEE 802.3ae-2002 specification

Xilinx provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. The core is designed to work with the latest Virtex™-5, Virtex-4 and Virtex-II Pro platform FPGAs and integrate seamlessly into the Xilinx design flow.

The 10GEMAC core is designed to the IEEE 802.3ae-2002 specification and supports the high-bandwidth demands of network Internet Protocol (IP) traffic on LAN, MAN and WAN networks.

The Xilinx 10GEMAC core is another of the SystemIO solutions which provide high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The MAC core performs the Link function of the 10Gb Ethernet standard. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI LogiCORE using the XGMII Interface.

关键特性

Designed to IEEE 802.3ae-2002 specification
Configured and monitored through an independent microprocessor-neutral interface
Optional Statistics counters
Configurable flow control through MAC Control pause frames; symmetrically or asymmetrically enabled
Generate customized core using the CORE Generator™ technology
Cut-through operation with minimum buffering for maximum flexibility in 64-bit client bus interfacing
Ability to generate core with no physical interface to allow users to connect the PHY-side interface of the core to user logic
Powerful EtherStats-based statistics gathering
Programmable Interframe Gap
Custom preamble preservation mode
Supports Deficit Idle Control (DIC) for max. data throughput
Maintains minimum IFG under all conditions and line rate performance
Remote Fault/Local Fault signaling at the Reconciliation Sublayer

Support Features

VLAN frames to specification IEEE 802.3-2002
Jumbo frames of any length
LAN/WAN (OC-192c data rate) functionality through open loop rate control
Generating Transmitter-only and Receiver-only implementations of the core

Interface Features

XGMII to PHY layer
Optional serial MDIO management interface
Uses Virtex-II Pro/Virtex-4/Virtex-5 digital clock management to implement XGMII timing

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Xilinx 以太网解决方案

What are the new features in the 10GEMAC LogiCORE™ IP?

Support for ISE™ 10.1.3 software

Which interfaces does the 10GEMAC LogiCORE IP support?

Ten Gigabit Media Independent Interface (XGMII) running at 156.25 MHz DDR to provide up to 10 Gbps total bandwidth
An internal FPGA interface which is 64-bit wide SDR running at 156.25 MHz to provide up to 10Gbps total bandwidth

Which Xilinx FPGA families and speed grades does the 10GEMAC core support?

Virtex™-5 (-1)
Virtex-4 (-10)
Virtex-II Pro (-5)

Which Xilinx Software version supports this core?

The files for the core itself are shipped in CORE Generator™ 10.1 IP Update 3. Xilinx ISE 10.1

What are the target applications for this product?

The 10GEMAC core is ideally suited for the development of Gigabit communications and storage equipment. Applications include switches, routers, servers, and network backbones.

With which PHYs is the 10GEMAC compatible?

The 10GEMAC core is designed to be compatible with industry standard PHYs with XGMII interfaces.

What is the availability, cost and licensing terms for the 10GEMAC core?

The 10GEMAC core is available now. The parameterizable core is configured through a CORE Generator™ GUI and licensed via the Xilinx IP site license. Purchase of the core entitles you to any additional updates which may be released for a period of one year from the date of purchase. Instructions for downloading the core can be found in the product lounge for this core. Licensing information, as well as information on all other Xilinx IP products, can be found on the Xilinx IP Center. Please contact your distributor or Xilinx FAE for pricing information.

Are there any restrictions for the core?

The pinouts for both the XAUI and XGMII configurations of the core are relatively flexible. The main restrictions are those imposed by the target device family selected and are described briefly in the 10GEMAC datasheet. Further details can be found in the Virtex-II Pro Platform FPGA User Guide, Virtex-4 Platform FPGA User Guide , and Virtex-5 Platform FPGA User Guide.
Very briefly, for the XGMII Configuration:
- All Vref pins must be connected externally to 0.75V for HSTL_I
- IOs should be grouped according to clock domains.
- If at all possible, the XGMII interface pins should be located on I/O banks on the East and West edges of the chip to improve the timing on the pins.

Has the 10GEMAC core been verified on hardware?

Xilinx has completed hardware verification of the 10GEMAC with XGMII PHY side interface at the University of New Hampshire Interoperability Lab (UNH IOL). Virtex-II Pro devices configured with XAUI interfaces (available as standalone core) have also been successfully tested for interoperability at UNH with a number of 10GE equipment vendors and PHYs during three separate XAUI group tests in October 2002, January 2003, and May 2003 on both the Xilinx ML321 and ML330 Virtex-II Pro development boards. (See the press release regarding the October 2002 group test.)
Contact your local Xilinx FAE to request a copy of the UNH reports for the 10GEMAC.

Are there any features that can be omitted to reduce the resource utilization of the core?

Statistics counters. If these counters are omitted, a configuration vector is provided to allow you to generate your own statistics.
Management interface
Transmitter block
Receiver block

How can I evaluate the core?

To try out the 10 GEMAC customization GUI and generate a gate level SimPrim library model which you can use to functionally evaluate the core in your system ("Simulation-only Evaluation"), follow the instructions regarding Xilinx ISE software, Service Pack levels, and IP Update installation requirements described here.
If you additionally wish to perform a Full System Evaluation in hardware, please contact your local Xilinx FAE to file a request.

Where can I find a list of known issues?

See IP Release Notes for known issues, new features and patches

What other Ethernet solutions does Xilinx provide?

The 10GEMAC core is part of the Xilinx Platform FPGA SystemIO solution, which addresses all aspects of system connectivity in high-performance designs. Xilinx provides the most comprehensive Ethernet MAC offerings in the programmable industry. In addition to the 10GEMAC core, Xilinx also provides:
- a XAUI standalone core
- a 1 Gb Ethernet MAC core with a choice of GMII or RGMII
- 1000BASE-X PCS with Ten Bit Interface, or integrated 1000BASE-X PCS/PMA or SGMII, a PLB Gb Ethernet MAC, Tri-Mode Ethernet (1000/100/10) MAC core or 10/100 Ethernet MAC core with choice of OPB or PLB interface for embedded MicroBlaze and PowerPC solutions.
- Tri-Mode Ethernet MAC core with a choice of GMII or RGMII
View a complete listing of Xilinx Ethernet IP solutions.

10 Gigabit Ethernet Media Access Controller (10GEMAC)

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支持器件系列

需求

Designed to the IEEE 802.3ae-2002 specification

关键特性

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